////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 14.7
//  \   \         Application : xaw2verilog
//  /   /         Filename : sys_shift.v
// /___/   /\     Timestamp : 11/03/2014 15:20:51
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: xaw2verilog -st E:/Work/TS_VHDL/M8/VG803_G01_DEMO8/ipcore_dir/sys_shift.xaw E:/Work/TS_VHDL/M8/VG803_G01_DEMO8/ipcore_dir/sys_shift
//Design Name: sys_shift
//Device: xc3s400a-4ft256
//
// Module sys_shift
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.87 ns
`timescale 1ns / 1ps

module sys_shift(CLKIN_IN, 
                 RST_IN, 
                 CLKFX_OUT, 
                 CLKIN_IBUFG_OUT, 
                 CLK0_OUT, 
                 CLK90_OUT, 
                 CLK180_OUT, 
                 CLK270_OUT, 
                 LOCKED_OUT);

    input CLKIN_IN;
    input RST_IN;
   output CLKFX_OUT;
   output CLKIN_IBUFG_OUT;
   output CLK0_OUT;
   output CLK90_OUT;
   output CLK180_OUT;
   output CLK270_OUT;
   output LOCKED_OUT;
   
   wire CLKFB_IN;
   wire CLKIN_IBUFG;
   wire CLK0_BUF;
   wire CLK90_BUF;
   wire CLK180_BUF;
   wire CLK270_BUF;
   wire GND_BIT;
   
   assign GND_BIT = 0;
   assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
   assign CLK0_OUT = CLKFB_IN;
   IBUFG  CLKIN_IBUFG_INST (.I(CLKIN_IN), 
                           .O(CLKIN_IBUFG));
   BUFG  CLK0_BUFG_INST (.I(CLK0_BUF), 
                        .O(CLKFB_IN));
   BUFG  CLK90_BUFG_INST (.I(CLK90_BUF), 
                         .O(CLK90_OUT));
   BUFG  CLK180_BUFG_INST (.I(CLK180_BUF), 
                          .O(CLK180_OUT));
   BUFG  CLK270_BUFG_INST (.I(CLK270_BUF), 
                          .O(CLK270_OUT));
   DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(25), 
         .CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(8.000), 
         .CLKOUT_PHASE_SHIFT("NONE"), .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), 
         .DFS_FREQUENCY_MODE("LOW"), .DLL_FREQUENCY_MODE("LOW"), 
         .DUTY_CYCLE_CORRECTION("TRUE"), .FACTORY_JF(16'hC080), 
         .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) DCM_SP_INST 
         (.CLKFB(CLKFB_IN), 
                       .CLKIN(CLKIN_IBUFG), 
                       .DSSEN(GND_BIT), 
                       .PSCLK(GND_BIT), 
                       .PSEN(GND_BIT), 
                       .PSINCDEC(GND_BIT), 
                       .RST(RST_IN), 
                       .CLKDV(), 
                       .CLKFX(CLKFX_OUT), 
                       .CLKFX180(), 
                       .CLK0(CLK0_BUF), 
                       .CLK2X(), 
                       .CLK2X180(), 
                       .CLK90(CLK90_BUF), 
                       .CLK180(CLK180_BUF), 
                       .CLK270(CLK270_BUF), 
                       .LOCKED(LOCKED_OUT), 
                       .PSDONE(), 
                       .STATUS());
endmodule
